The invention relates to a circuit arrangement for establishing conference connections comprising conference units linked to form a loop, and wherein:
at least one sum codeword passes from one conference unit of the loop to the next; PA0 a sum codeword is formed from sample values of the signals of all the participants in a conference; PA0 and each conference unit comprises means by which the sum codeword is updated by the use of the actual sample value and by which a conference signal for the allocated conference is formed from the sum codeword. PA0 the function of one or more conference units is taken over by a programmed processor; PA0 an interface circuit controls the conference signal input and output by means of write and read commands by which each of the programmed processors is actuated; PA0 one of the processors writes each sum codeword that has been updated into an input memory of the next processor which reads the word from this memory as required; PA0 each updated sum codeword is transformed into a test word and, at a later instant, the contents of the input memory of the next processor are overwritten by the test word whereby the next processor reads the test word from this memory, compares the sum codeword previously contained in this memory to the test word and produces an alarm signal, if necessary; PA0 successive processors perform the program items of updating the sum codeword and comparing the sum codeword to the test word in a time offset order.
A circuit arrangement of this type is described in DE 39 01 909 (filing date: Jan. 24, 1989). In this arrangement, however, there are no provisions to verify whether the sum codewords pass through the loop in an error-free manner.